1. Field of the Invention
The present invention relates to a main memory control system for controlling the configuration of a plurality of unit memories in a main memory for use in a data processing system.
2. Description of Prior Art
The configuration of a main memory forming a part of a conventional data processing (DP) system is achieved by using software instructions. An address space of the main memory with this memory configuration is, however, not always continuously connected over the entire memory area from the minimum logical address to the maximum logical address in the address space of the main memory at any given time. For example, in a specific part of the address space, a unit memory (e.g. block of memory, page etc.) in the main memory which has initially been allocated to correspond to a logical address is often disconnected from the DP system because of some trouble or failure of the unit memory, resulting in the discontinuity of the address space in the main memory.
Such discontinuities in the address space (i.e. in the mapping of the sequence of logical addresses to physical memory locations) can present problems when a DP system is interrupted during operation by troubles in the central processing unit (CPU), the input/output (I/O) control unit, the main memory, and the I/O devices due to power failure, abnormal temperature, fire flood, lightning, of earthquake. After the trouble is cured, the operating system is restarted (by a procedure commonly called a "restart" or "rescue" routine) so as not to effect various services. To this end, a rescue type initial program load command is executed in the DP system so that operation can be resumed from the last rescue point. However, at this time point, the continuity of the address space of the main memory is not ensured as described above. Execution of the rescue routine requires the mapping of the sequence of logical addresses to operative unit memories to be continuous. Therefore, it is impossible to perform the rescue type initial program load (RIPL) command for all the memory areas of the main memory connected in the DP system unless the main memory is reconstructed by using software instructions. For this purpose, before the execution of the RIPL command, the main memory must be reconstructed by using software instructions in order to ensure the continuous address space. Alternatively, the RIPL command is executed for each separate unit memory where a continuous address space is ensured. The main memory is then reconstructed or reallocated by the software instructions loaded in response to the RIPL command.
An object of the present invention is, therefore, to provide a novel hardware structure of a main memory control system which can execute the RIPL for all the memory areas connected in the DP system before said program load operation is performed.